Analog & Mixed-signal designs


With the spurt in demand for analog ICs in consumer electronics, IoT, automotive, medical/health electronics, etc., analog and mixed-signal IC shipments are all set to outpace digital. Instead of adding traditional discrete components for their products, design companies are adding more and more analog functionality in silicon. As a result the number of analog modules in a SoC has increased at a significant pace.

With design teams getting dispersed at multiple sites, there is a growing need for analog and digital designers to collaborate even more efficiently. A narrow time-to-market window makes design collaboration and designer productivity essential for product success.

SOS from ClioSoft is the leading design data collaboration platform for SoC design teams. It is integrated into analog design tools from all major electronic design automation (EDA) vendors, enabling design teams to build, collaborate and manage their designs efficiently from the EDA tool cockpit. Using SOS, designers can effectively manage the different versions of schematic, layout and other associated cell views, review the differences in schematic or layout and share their design data with other designers located either locally or across multiple sites.

Design teams can define their own custom handshake protocols to manage complex design flows and improve designer productivity. An easy-to-use environment, ability to customize to individual requirements, support for different work models and robust performance built for large design data sizes make SOS ideal for analog and mixed-signal designers.

Mixed-Signal Methodology Guide


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ClioSoft wrote the chapter on SoC design data management in Cadence’s Mixed-Signal Methodology Guide. Register to receive an electronic copy of this chapter

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SOS - Cadence® Virtuoso® Platform

SOS Virtuoso from ClioSoft is the leading SoC design management software for analog and mixed-signal design teams using the Cadence Virtuoso platform. It enables analog designers to build and collaborate with other team members, located either locally or at remote design sites, on the same design, from concept to GDSII.

SOS Virtuoso is built on the powerful SOS7 design platform from ClioSoft, to meet the unique requirements of semiconductor design teams. The requirements of SoC designs today - high design complexity, different EDA tools from numerous vendors, extremely large binary tool databases and a complex design flow - is quite different from the needs of the software teams. These needs cannot be met by the tools commonly used in the software industry. Higher designer productivity and ease of use also necessitates a tight coupling between the different tools and the design management platform to ensure ease in managing the design data. SOS Virtuoso provides such a tight integration between the Cadence Virtuoso platform and ClioSoft's SOS7 SoC design management platform.

SOS Virtuoso provides the following features:

The SOS7 platform improves design flow efficiency and design team productivity by providing an eco-system where designers can use tools from different vendors to design digital, analog and RF design modules. Its scalable architecture and multi stream hyper data transfer technology enables design teams to customize as needed to meet the requirements of their design methodology without compromising on performance or disk space. SOS7 provides flexible release and derivative management along with revision control to meet the requirements of any design flow. It maintains a correlation between the defects and changes made in the design to fix the defect. SOS7 supports commonly used bug-tracking systems such as Jira, Trac, Bugzilla and Fusion Forge. It also provides semiconductor companies the flexibility to make changes in their choice of EDA tools without having to worry about the integration of the tools with the data management platform.

SOS - Synopsys® Custom CompilerTM/Laker3TM

SOS Custom Compiler from ClioSoft is the leading SoC design management software for analog and mixed-signal design teams using Synopsys Galaxy Custom Compiler or Synopsys Laker3. It enables analog designers to create their designs while collaborating with other team members, located either locally or at remote design sites, on the same SoC design, from concept to GDSII.

It is built on the powerful SOS7 design platform from ClioSoft, to meet the unique requirements of semiconductor design teams. The requirements of SoC designs - design complexity, different EDA tools from numerous vendors, extremely large binary tool databases and a complex design flow - is quite different from the needs of the software teams, and cannot be met by the tools commonly used in the software industry. It also mandates a tight coupling between the different tools and the design management platform to ensure ease in managing the design data. SOS Custom Compiler provides a tight integration between the Synopsys Galaxy Custom Compiler or Laker3 and ClioSoft's SOS7 SoC design Management platform to ensure higher designer productivity.

SOS Custom Compiler provides the following features

The SOS7 platform improves design flow efficiency and design team productivity by providing an eco-system where designers can use tools from different vendors to design digital, analog and RF design modules. It's scalable architecture and multi stream hyper data transfer technology enables design teams to customize as needed to meet the requirements of their design methodology without compromising on performance or disk space. SOS7 provides flexible release and derivative management along with revision control to meet the requirements of any design flow. It maintains a correlation between the defects and changes made in the design to fix the defect. SOS7 supports commonly used bug-tracking systems such as Jira, Trac, Bugzilla and Fusion Forge. It also provides semiconductor companies the flexibility to make changes in their choice of EDA tools without having to worry about the integration of the tools with the data management platform.

SOS - Mentor Graphics® Pyxis

SOS Pyxis from ClioSoft is the only commercial SoC design management software for analog and mixed-signal design teams using Mentor Graphics Pyxis or ICSudio. It enables analog designers to build and collaborate with other team members, located either locally or at remote design sites, on the same design, from concept to GDSII.

It is built on the powerful SOS7 design platform from ClioSoft, to meet the unique requirements of semiconductor design teams. The requirements of SoC designs - design complexity, different EDA tools from numerous vendors, extremely large binary tool databases and a complex design flow - is quite different from the needs of the software teams, and cannot be met by the tools commonly used in the software industry. It also mandates a tight coupling between the different tools and the design management platform to ensure ease in managing the design data. SOS Pyxis provides a tight integration between the Mentor Graphics Pyxis and ClioSoft's SOS7 SoC design management platform to ensure higher designer productivity.

SOS Pyxis provides the following features

The SOS7 platform improves design flow efficiency and design team productivity by providing an eco-system where designers can use tools from different vendors to design digital, analog and RF design modules. It's scalable architecture and multi stream hyper data transfer technology enables design teams to customize as needed to meet the requirements of their design methodology without compromising on performance or disk space. SOS7 provides flexible release and derivative management along with revision control to meet the requirements of any design flow. It maintains a correlation between the defects and changes made in the design to fix the defect. SOS7 supports commonly used bug-tracking systems such as Jira, Trac, Bugzilla and Fusion Forge. It also provides semiconductor companies the flexibility to make changes in their choice of EDA tools without having to worry about the integration of the tools with the data management platform.

Visual Design Diff

ClioSoft’s Visual Design Diff (VDD) gives users the power to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in the design editor. Identifying differences between different versions of the schematic or layout is extremely useful in design flows or ECO flows when the designer is narrowing down the changes made to determine the cause of failure.

VDD works with the Cadence Virtuoso® platform and detects changes that include any modifications to nets, instances, layers, labels and even properties. VDD can highlight the differences between two versions of the same cell-view or between any two cell-views of the same type. Supported view types include schematics, layouts and Verilog.

VDD comes integrated with ClioSoft’s SOS7 design management platform but can also be deployed standalone with any other design management system or even if no design management system is being used. The ability to quickly and visually identify changes has several uses and benefits:

Engineers can check changes before publishing a new revision of the cell-view.

Managers can review changes before approval.

Layout engineers can identify modifications made to schematics.

Layout ECOs can be reviewed without the time consuming process of generating and comparing GDS.