Implementing a Design Reuse Methodology
Using a Design Data Management System

Samir Palnitkar, Chief Technical Officer

Integrated Intellectual Property Inc.
1765 Scott Blvd, Suite #208, Santa Clara, CA 95050


Development for Design Reuse is a critical challenge facing design houses and semiconductor vendors today. Designs are broadly classified into two categories: legacy designs and current designs. For the past decade, companies were focusing on creating a design and getting it to work for their immediate product. However, with a shift to the "system-on-chip" methodology, it has become crucial, for competitive reasons, that every design be done with an "IP paradigm" or "Design Reuse" in mind, so that it can be integrated quickly into a larger system-on-chip. However, this approach requires a completely different methodology and mindset.

This paper explores the details of a complete IP methodology that revolves around development standards, scripts, release mechanisms and shrink-wrapped packaging using "SOS", a software system for design data management.

  1. Introduction
    1. What is the IP paradigm?
      Traditionally, chips have been designed with a goal to get them to work. Engineers pay lots of attention to aspects that are very specific to a particular project. However, often engineers do not look beyond the horizon of the current project. Due to faster chips, increased competition and shorter design cycles, companies have been forced to reevaluate this narrow vision. Therefore, it has become imperative that each company does the designs in such a way, that these designs can not only be used for the current project, but also for the future projects. This approach requires engineers to build every design as a synthesizable core. We call this the "IP paradigm".

      Companies need to design with the IP paradigm so that they can be competitive in the marketplace. Design cycles are becoming increasingly shorter and levels of integration are rising exponentially. If a company does not move to an IP paradigm, it will be left with costly products that are late to market. In addition, the structured approach will help designs to be done much quicker.

    2. How does it affect the design process?
      The first time the block is being developed, engineers need a very structured methodology that promotes design reuse. It takes a little longer to set up the methodology. However, once it is set up, the process of design creation is a lot more efficient and methodical. There is less confusion about how the design tasks are partitioned and engineers can work independently to get their blocks working before integrating them into the design.
    3. How is it applied to legacy designs?
      Legacy designs that have not been designed with an "IP Paradigm" will need to be converted over to an IP methodology so that these designs can be reused within the company or sold to other companies. We currently use a "cleaning room" methodology to clean and package existing IP.
      Legacy Designs
    4. How will it be applied to new designs?
      New designs will have to be developed as synthesizable cores. They will then be converted to silicon for a specific project. The project thus becomes an internal customer of the synthesizable core. The core can also be sold to external customers.
      New Designs


  2. Managing IP design data This section discusses how we handle IP design data.
    1. Handling Design Complexity
      Designs are increasing complex. Multiple engineers have to work together on the same design. It is not only important to keep track of the HDL files that make up the design but also all the test benches, make files, scripts, stimulus, and other data files necessary to verify and synthesize the design. So a design may be made up of hundreds or even thousands of files. The burden of managing this data is even more complicated for IP design. You also have to deal with making multiple releases to customers and making patches to old releases. Sometimes you may also have to do special enhancements for some customers. In order to effectively manage IP design data we need to:
      • Manage many hundreds of files spread over multiple directories.
      • Revision control all source files.
      • Have multiple engineers work collaboratively.
      • Make sure that only lint free HDL files are checked in.
      • Allow different engineers to work on different activities such as verification, synthesis, release, patch, etc. concurrently.
      • Make high quality releases and track the revisions of all the files and directories that make up a release.
      • Recreate any previous release exactly with the same directory structure and revision of files so customer problems can be replicated.
    2. What is SOS?
      SOS is a graphical design data management product from ClioSoft, Inc. (, which we have used to effectively manage IP development and release over the past year. SOS has helped us enhanced the productivity of our design team and improved the quality of our product.

      The graphical nature of the tool and the simple usage paradigm makes it very easy for new engineers to get started on a project. It has a centralized and secure design repository and provides revision control, manages directory hierarchy and tracks releases. Each engineer works in her/his own work area or sandbox, which is created through SOS by specifying a rule to select revisions of files. This allows one engineer to work on the latest enhancements while a second engineer is creating a patch release and a third engineer is running a long synthesis job concurrently without affecting each other.

      SOS Window

      In addition to the visual representation of the entire project SOS has a set of flags, which automatically improve collaboration and quality. Furthermore, the customizability of SOS allows us to automatically run Verilint before a verilog file is checked in. Due to these collaboration features our engineers never lose time struggling with common errors like tracking down who forgot to check a file in or added changes which are not lint free. When making a release we know exactly what we have and that all previous patch fixes have been incorporated into this new release. The following figure shows the data management of a complete AGP/PCI IP development system.

  3. IP Development Methodology
    This section examines the various aspects of our development methodology for new IP cores.
    1. Design for reuse
      This step is the first part of our reuse methodology. In this step, there is a lot of planning before, we actually do any coding or implementation. We plan for each step of the following methodology.