News & Events

ClioSoft at Design Automation Conference 2016

Demonstrating SoC Design and IP Management Platform

FREMONT, Calif., May 24, 2016 – At DAC 2016, ClioSoft, the pioneer and leading developer of system-on-chip (SoC) design configuration and enterprise intellectual property (IP) management solutions for the semiconductor industry, will demonstrate the SOS Design Management Platform and IP Management solutions as well as participating on a panel in the IP Track. SOS is the EDA industry’s most widely installed design data and enterprise IP management solution for analog, RF, digital and mixed-signal designs. ClioSoft’s SOS platform is integrated with major EDA flows from Cadence Design Systems®, Keysight Technologies, Mentor Graphics and Synopsys®.

The 53rd DAC will be held this year from June 5 to June 9 in the Austin Convention Center in Austin, Texas.

PANEL - How Do We Make IP Reuse Work?

Moderated by Brian Fuller, editor-in-chief, ARM, Inc.

The plug-and-play concept of using IP to create SoCs has not taken off as expected. Representatives from the design, provider and semiconductor communities will discuss the challenges that have to be overcome and what can be done to improve IP reuse for analog and digital designs. Will emerging technologies such as 3D stacking help? What is happening with new languages and proposed standards? Will an IP management system that lets designers find the right existing IP and track its previous success help?

Representatives from the design, provider and semiconductor communities will discuss what ails the IP industry and what can be done to improve IP reuse for analog and digital design. For more detail, click here.

  • Ranjit Adhikary - ClioSoft, Inc., Fremont, CA
  • Lisa Minwell - eSilicon Corp., San Jose, CA
  • Rwik Sengupta - Samsung Semiconductor, Inc., Austin, TX
  • John Koeter - Synopsys, Inc., Austin, TX

When: 3:30 to 4:30 pm on Wednesday, June 8, 2106
Where: Room 18AB, Austin Convention Center



The SOS Design Management Platform from ClioSoft is integrated with tools from all major EDA vendors, providing the only cohesive design environment for all types of digital, analog, RF and mixed-signal designs. SOS facilitates multi-site design collaboration and includes, among other features, integrated revision control, release and derivative management and interfaces to commonly-used bug tracking systems.

At DAC 2016, ClioSoft will showcase how the tight coupling of SOS with major design flows empowers design engineers to manage their design data directly from their familiar design cockpit. This enables design teams to be productive and efficient while reducing the possibility of design re-spins due to incorrect configurations.

Visual Design Diff (VDD) from ClioSoft enables users to quickly compare design differences in schematics, layout and RTL by graphically highlighting the differences. A hierarchical diff option allows all differences for the entire design hierarchy below the selected view to be flagged.

IP Management from ClioSoft helps accelerate SoC development by managing internal and third-party IPs. It eases the pains associated with creating IPs, determining IP suitability and tracking the IPs across an enterprise.

When: 10:00am to 6:00pm from Monday, June 6 to Wednesday, June 8, 2016. Register to arrange a private demonstration of their products.
Where: Booth 519, Austin Convention Center

For more Information
Linda Marchant,
Cayenne Communication



About ClioSoft Inc.

ClioSoft, Inc. is the pioneer in the field of SoC design configuration management and enterprise IP management solutions for the semiconductor industry. Built exclusively for hardware design engineers, with flexibility to adapt to complex flows, ease of use and robustness as the main drivers, ClioSoft’s SOS Design Collaboration Platform empowers design teams located at multiple sites to collaborate efficiently on complex RF, analog, digital and mixed-signal designs.

Using SOS, design teams can streamline the development of complex SoC designs from design specification to tapeout by efficiently sharing and managing their design data across different design centers using a distributed, fault-tolerant architecture. To handle the requirements of complex SoC design flows, the SOS platform is integrated with major EDA flows.

The sole objective of ClioSoft’s collaborative IP management solution is to improve design reuse within a company. ClioSoft helps semiconductor companies catalog and manage internal and third-party IPs, providing an easy-to-use administration and user cockpit to manage the process of creating IPs and their derivatives, their lineage, IP licensing, security, and issue and defect tracking.

* All trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.