Increased complexity in SoCs & PDKs coupled with convoluted design methodologies has resulted in an increase in the number of designers at most semiconductor companies. To tapeout successfully within the prescribed schedules, it is essential to ensure smooth handoffs and efficiency in design collaboration. Design team managers and engineers now need quick answers to questions such as
- What design changes have been checked in this week?
- What are the projects using this version of the IP?
- Is the layout for this design DRC/LVS clean?
- The design was working yesterday. What changed?
- What is the difference between the two versions of this layout?
Without the presence of a SoC design data management system and a formal process to collaborate among geographically dispersed designers, a lot of productivity is wasted and spurious errors may result which could take considerable time to rectify. Join the webinar where we showcase a non-intrusive flow for both local and remote design teams to effectively collaborate on their IPs/SoCs by using ClioSoft's SOS7 Design Management Platform integrated with EDA tools from major vendors.