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Managing Your IPs & SoC Design Data for Successful Tapeouts

When:
Tuesday, April 30, 2019 | 9:15 am - 4:15 pm
Location:
West Lagoon Hotel, Netanya, Israel

The increase in design complexity along with tight design schedules has led to an increase in the number of designers in most semiconductor companies. Ad hoc methodologies that worked in the past among SoC design groups do not necessarily work correctly today due to the large number of designers whose work has to coordinated across multiple sites. Tight design schedules and increased complexity also requires an ecosystem that enables designers to reuse internal/3rd party IPs/PDKs efficiently and ascertain their quality prior to use.

Without the presence of a design data & IP management system and a formal process on how to collaborate among geographically dispersed designers and design groups, a lot of productivity is wasted and engineers may create spurious errors that take considerable time to rectify.

Join us on Tuesday, April 30th, 2019 at the seminar and listen to how our customers use ClioSoft’s SoC design management platform and IP reuse ecosystem to tapeout their SoCs successfully.

This seminar is free of charge, but due to the limited availability of seats, pre-registration is required. Registration is pending ClioSoft’s approval. For more information, please contact Uri Farkash.

Agenda
9:15 am - 9:45 am Check-in and light breakfast
9:45 am - 10:00 am Welcome and Introduction to ClioSoft, AST and the speakers
Eli Geva, AST, CEO and Uri Farkash, AST, ClioSoft Sales Manager in Israel
10:00 am - 10:15 am Keynote address
Ranjit Adhikary, ClioSoft, VP Marketing
10:15 am - 11:30 am Managing your designs for successful tapeouts
Ioannis Syranidis, ClioSoft, Technical Account Manager
11:30 am - 11:45 am Break
11:45 am - 12:15 pm PDK development and release flow using SOS7 and designHUB
Ofer Tamir, TowerJazz, Sr. Director Design Environment & Support and Ronen Hasnes, Design Kit SH
12:15 pm - 12:45 pm System design enablement with Virtuoso advanced design and methodologies
Yonatan Kliger, Cadence Design Systems, AE Director
12:45 pm - 1:15 pm PnR flow using UDMA and project modular cache
Evgeniy Makarov, Valens, CAD Manager
1:15 pm - 2:15 pm Lunch and networking
2:15 pm - 2:35 pm Design data management in Custom Compiler using Cliosoft SOS7
Isaac Zafrany, Synopsys, AMS & Custom Group Manager
2:35 pm - 2:55 pm SOS7 – Integration and data management first aid
Ran Rosenzweig, Inomize, Director of Analog & Layout Design
2:55 pm - 3:15 pm Improving design productivity for RF designers using Keysight ADS
Meidan Borochov, Keysight, EDA Sales Manager
3:15 pm - 4:00 pm Reusing your IPs to develop SoCs faster
Ioannis Syranidis, ClioSoft, Technical Account Manager
4:00 pm - 4:15 pm Thanks and lucky prize draw
Uri Farkash, AST, ClioSoft Sales Manager in Israel
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About ClioSoft Inc.

ClioSoft® is the pioneer and leading developer of enterprise system-on-chip (SoC) design configuration and IP-management solutions for the semiconductor industry. The company provides two unique platforms that enable SoC/IP design-management and reuse.

The SOS7 platform is the only design-management solution for multi-site design collaboration for all types of designs – analog, digital, RF and mixed-signal. The designHUB® platform provides a collaborative IP reuse ecosystem for enterprises.

ClioSoft customers include the top 20 semiconductor companies worldwide. The company is headquartered in Fremont, CA with sales offices and distributors in the United States, United Kingdom, Europe, Israel, India, China, Taiwan, South Korea and Japan. For more information visit www.cliosoft.com


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