The increase in design complexity along with tight design schedules has lead to an increase in the number of designers in most semiconductor companies. Ad hoc methodologies that worked in the past among SoC design groups do not necessarily work correctly today due to the large number of designers whose work has to coordinated across multiple sites. Tight design schedules and increased complexity also requires an ecosystem that enables designers to reuse internal/3rd party IPs/PDKs efficiently and ascertain their quality prior to use.
Without the presence of a design data & IP management system and a formal process on how to collaborate among geographically dispersed designers and design groups, a lot of productivity is wasted and engineers may create spurious errors that takes considerable time to rectify.
Join us on Tuesday, April 30th, 2019 at the seminar and listen to how our customers use ClioSoft’s SoC design management platform and IP reuse ecosystem to tapeout their SoCs successfully.
This seminar is free of charge, but due to the limited availability of seats, pre-registration is required. Registration is pending ClioSoft’s approval. For more information, please contact Uri Farkash.
|9:15 am - 9:45 am||Check-in and light breakfast|
|9:45 am - 10:00 am||Welcome + Introduction of ClioSoft, AST and Speakers|
|10:00 am - 10:15 am||Keynote|
|10:15 am - 11:30 am||ClioSoft SOS Presentation & Demo|
|11:30 am - 11:45 am||Break|
|11:45 am - 12:15 pm||Customer Track|
|12:15 pm - 12:45 pm||Partner Presentation|
|12:45 pm - 1:15 pm||Customer Track|
|1:15 pm - 2:15 pm||Lunch & Networking|
|2:15 pm - 2:45 pm||Customer Track|
|2:45 pm - 3:45 pm||ClioSoft designHUB Presentation & Demo|
|3:45 pm - 4:00 pm||Thanks and Lucky Prize Draw|