How to save yourself time and frustration.
In my experience, design engineers are zealous folks who want to extract every ounce of performance out of their design. They continue to make incremental changes to the design until the very end, as close to tape out as possible. Each change made to the design requires corresponding changes to be implemented in the layout.
If you are a design engineer, how do you answer this question from your mask layout designer: “So … what changes did you make now?”
If you have a good memory, you could perhaps list out all the changes you made to the schematic. Or, if you are meticulous, you are keeping a running list of the changes you make to the schematics throughout the project. You can now share the list with your layout designer. The problem here is that both of these processes are error-prone. It is only human to forget a minor change! For that reason, design engineering processes include multiple runs of Layout vs. Schematic (LVS) checking in the flow to catch mismatches between schematics and layouts. No doubt, the LVS jobs prevent blunders.
However, think of this from a productivity and efficiency point of view: a design engineer generates a TO-DO list for the layout designer with each version of the schematic by memory or discipline. The list has a fair chance of being inaccurate. The layout designer possibly implements changes based on an erroneous or incomplete list. Then the layout designer runs LVS jobs, only to find the mismatches, perhaps seeks clarification from the design engineers, makes the corresponding changes to the layout, and runs LVS again. It is not unreasonable to expect to iterate a couple of times in order to get it right.
Some experienced layout designers with an eye for detail are also good at spotting the difference between versions of schematics. It is always a pleasure to work with such folks because the iterations to understand what changes have happened is reduced significantly. However, even the best layout engineers find it a bit difficult to spot the changes in the attributes of devices. Missing an attribute change and not implementing it in the new version of the layout could impact the layout generated and lose productive hours of work.
Now, think about how much of your time did you spend doing this on the last project? Was it significant? Was it frustrating to iterate and get it right?
Cliosoft’s Visual Design Diff (VDD) tool can help a layout engineer get a quick and accurate answer to the question of what has changed in the schematic. Cliosoft VDD takes two schematics or schematic revisions as inputs and computes the changes between them. The mask layout engineer simply points the tool to the previous version of the schematic and the new one.
- In the native Cadence Virtuoso Schematic Editor window, the tool highlights new objects and deleted objects.
- The tool also highlights any modification made to the objects’ CDF properties – both system and standard.
- The interactive tool allows the layout engineer to filter objects of interest. For example, one might want to look at only the nets that have changed to plan the routing. There is a filter for that.
- The Cliosoft VDD tool also allows the user to focus on electrical changes. For example: in a schematic, if the designer moves a block to make it more human-readable, that does not warrant a change to the layout as it is considered a cosmetic change. Cliosoft VDD has an option not to display such cosmetic changes.
Cliosoft VDD is a tool specifically designed for design engineers and mask layout designers working on custom designs to write out a correct change list on-demand. The design engineers do not need to exercise and rely on their memory or write meticulous logs of activities. Yet, as you can see in the screenshot above, layout designers have the information they need to make changes to the layouts by simply pointing to the previous and current schematic versions, and the list of changes is generated. Also, in the schematic/layout editor window, the layout designer can visualize the changes in the schematic! Design engineers and layout designers now have a better way to collaborate with each other while ensuring that their schematics and layouts are always in-sync.
To summarize, the ability to Visualize the difference between two schematics provides the team with valuable productivity gains:
- Schematic design engineers do not need to keep or create a running list of changes they work on. This frees up time for the engineers to focus on optimizing the design.
- The layout designer can generate an accurate and precise list of the task they need to implement in layout. A layout designer can now plan their workdays better now that they have a task list.
- The Layout designers can now also provide more accurate estimated schedules to the project manager. The estimate is based on accurate data and therefore the project managers can assign a higher level of confidence when tracking the project schedules
In part two of this blog series, we will talk about how project managers can bring efficiency to an ECO. So stay tuned.