Keeping track of changes made during the ECO phase to avoid miscommunication and avoid unnecessary modifications.
In the last blog in this series, we talked about how VDD can help design and layout engineers work more efficiently. Communicating precise and accurate information is a key factor in improving productivity, estimates, and the planning process. Visualizing the changes makes it easier to follow the technical details.
The ECO (Engineering Change Order) phase is an important phase in the lifecycle of a design project. It is safe to assume that for pretty much every bleeding-edge project, the specification and/or implementation details change while the development is in process. ECOs can compensate for design bugs or changes to the design specification. Depending on the design methodology or flow, ECOs may happen pre-silicon or post-silicon. In some rare cases, the experienced design team even dares to tapeout the base layers while making changes to some metal layers.
When a team takes on the responsibility of an ECO, it is critical that each member of the team understands, agrees, and implements only specific changes. The design manager and layout manager both need to keep track of the fact that the team is implementing only the agreed-upon changes. Since the ECO phase is at the tail end of a project, there is often an enormous time pressure to not miss the deadline.
For the sake of illustration, let’s assume that the AFE (Analog Front End) is designed to satisfy the requirements. The layout team is almost done with the implementation of the said design. And the AFE is ready to be integrated with the rest of the chip. However, a last-minute change comes up. The chip integration team wants to increase the drive strength of the output stage of the AFE just by a little bit. The AFE team determines it is technically possible to do it by making a few minor changes. This can be done with an ECO. The team agrees to this change and starts to think about it.
Often seen is the following scenario…
Passionate engineers need to run additional simulations with more accurate parasitics after the design is done. The reason is that they have more accurate parasitics data after the layout is completed. Oftentimes this is a validation of the design that they came up with and it guides them to make a more efficient design in the next iteration.
In our illustration, let us take a case where the design engineer found a better way to fix an ESD parameter. His original solution was adequate, but this is way cooler! To an engineer, it seems like an obvious decision to include his change in the ECO. The simulation data may even make a strong case for it. However, from a design management perspective, does it make sense to include it in the ECO? While technically it may make total sense, there is often not enough time and resources to re-work upstream changes. Very often the design managers tend to be more cautious and choose not to incorporate last-minute changes to the design.
The design manager needs to make sure that these last-minute changes don’t accidentally make it into the ECO. One way to do this is to run a hierarchical check on the AFE top cell and make sure ONLY the agreed-upon schematics and layout are modified. How can this be achieved?
Cliosoft VDD has a hierarchical mode of operation that can be used in conjunction with tagged data.
Let’s say that the release candidate delivered to the integration team was tagged as “RC_1”. The design manager can run a hierarchical Visual Design Diff analysis report on the AFE top cell schematic and identify the cell that has been modified. The design manager can simply drill down each modified design object and inspect the changes that have happened since the RC_1 tag was applied. Visualizing the design changes with bold colors on a Cadence schematic or layout canvas is a very efficient way to identify the changes that have gone into effect.
In the scenario above, the power of Cliosoft VDD is a valuable asset in design collaboration. It gives the design manager the ability to keep track of the changes that are happening throughout the design hierarchy. It eliminates the potential for miscommunication as to what cell actually got modified.
Cliosoft VDD can be utilized in another interesting way in the ECO phase of the project. It can be used non-interactively with a command-line interface. If the design team has implemented an infrastructure for nightly regression infrastructure, the tool can accurately report the changes and progress. Very easily, the regression can raise a red flag if unexpected cells are modified. An alerting system like this is critical, especially when implementing large designs that have various IPs stitched together in the product.
To summarize, the ability to visualize or report the changes made since the last release candidate is a powerful tool in the design and layout managers’ arsenal.
- Visualization brings efficiency to communications. No emails to read, write, and interpret. Visual changes tell the exact story of what cell views in the hierarchy were modified.
- The layout designer can generate an accurate and precise list of the tasks needed to implement in the ECO. The layout designer can therefore plan their ECO phase and provide an accurate estimate of schedules for completing the ECO.
- The text reporting functionality can be integrated into automated alert systems to prevent teams from spending limited valuable time and resources on tasks that are not crucial for the current ECO.
In the third part of this blog series, we will talk about the importance of setting up a design flow that balances the quest for achieving perfection in design, while still keeping the project schedules on track.
